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Atari 600xl/800xl & 65816

This is my collection of notes on the Atari 600xl/800xl line as related to the 6502/6502C (SALLY) CPU and the 65816. At the moement please be careful with this information as it hasn't been verified.



The Atari SALLY (6502C) is a custom 6502 built for Atari to be used in the later versions of the A8 (Atari 8 Bit) computers. It can be found in some older Atari 800's (I think I have one) and in the 600xl/800xl through the later XE line. It differs in that the R/W line is moved to pin 35 instead of pin 34. Additionally there is a HALT line. This allows something like the ANTIC to halt the processor while the ANTIC access memory (DMA).

Since the older 400/800 line also uses the same ANTIC processor but with a normal 6502 (6502B? 65B02?) their schematics contain the HALT circuit built in TTL chips.

           /=============\                     /=============\                    /=============\
       VP  I1          40I RST            Vss  I1          40I RST           Vss  I1          40I RST
      RDY  I2          39I VDA            RDY  I2          39I o2 (OUT)      RDY  I2          39I o2 (OUT)
    ABORT  I3          38I M/X       o1 (OUT)  I3          38I SO       o1 (OUT)  I3          38I SO
      IRQ  I4          37I o2 (IN)        IRQ  I4          37I o2 (IN)       IRQ  I4          37I o2 (IN) o0
       ML  I5          36I BE              NC  I5          36I NC             NC  I5          36I Halt
      NMI  I6          35I E              NMI  I6          35I NC            NMI  I6          35I R/W
      VPA  I7          34I R/W           SYNC  I7          34I R/W          SYNC  I7          34I NC
      VDD  I8          33I D0/BA0         Vdd  I8          33I D0            Vdd  I8   Atari  33I D0
       A0  I9  W65C816 32I D1/BA1          A0  I9   6502   32I D1             A0  I9   6502C  32I D1
       A1  I10         31I D2/BA2          A1  I10         31I D2             A1  I10  SALLY  31I D2
       A2  I11         30I D3/BA3          A2  I11         30I D3             A2  I11         30I D3
       A3  I12         29I D4/BA4          A3  I12         29I D4             A3  I12         29I D4
       A4  I13         28I D5/BA5          A4  I13         28I D5             A4  I13         28I D5
       A5  I14         27I D6/BA6          A5  I14         27I D6             A5  I14         27I D6
       A6  I15         26I D7/BA7          A6  I15         26I D7             A6  I15         26I D7
       A7  I16         25I A15             A7  I16         25I A15            A7  I16         25I A15
       A8  I17         24I A14             A8  I17         24I A14            A8  I17         24I A14
       A9  I18         23I A13             A9  I18         23I A13            A9  I18         23I A13
      A10  I19         22I A12            A10  I19         22I A12           A10  I19         22I A12
      A11  I20         21I Vss            A11  I20         21I Vss           A11  I20         21I Vss
           \=============/                     \=============/                    \=============/


ML: Memory Lock line (pin 5) is asserted low during the execution of the read-modify-write (asl,dec,inc,lsr,rol,ror,trb, and tsb instructions to inform other ics that the bus may not be claimed yet. VP: Vector Pull is asserted whenever any of the hardware vector address's are being accessed during an IRQ. Abort: An input. When asserted caused the current instruction to be aborted. VPA/VDA: Valid Program Address and Valid Data Address. These two signals extend on the 6502 SYNC line - to better handle DMA schemes. VPA VDA 0 0 - Internal Operation 0 1 - Valid program address 1 0 - Valid data address 1 1 - Opcode fetch M/X: Memory and Index lines. These signals are multiplexed on pin 38. M is available during phase zero and X during Phase one. These two signals reflect the contents of the status register m and x flags, allowing other devices to decode opcode fetches. E: Emulation pin. This signal reflects the state of the processors emulation bit (E).

The differences

The main differences between both processors are: Pin 65816 6502 SALLY (6502C) --- ------- -------- -------- 1 VP GROUND GROUND (Vss) 3 ABORT CLK1 CLK1 (o1 OUT aka PH1) 5 ML NC NC 7 VPA SYNC SYNC 34 R/W R/W NC (Swapped with 35) 35 E NC R/W (Swapped with 34) 36 BE NC Halt 38 M/X SO SO 39 VDA CLK2 CLK2 (o2 OUT aka PH2) CLK1 - o2 (OUT) CLK2 - o1 (OUT)

The 65816 lacks the CLK1 (PH1) and CLK2 (PH2) clock signals so we have to provide them ourselves. That's where two 74F04 inverters come in view.

(PH0) --|>o--(PH1)--|>o-- (PH2)

ABORT and BE are 816-specific inputs and only need a pull-up resistor. These resistors enable you to use these inputs later. If you are sure you don't need them, just omit the resistors and connect these inputs directly to +5V (pin 8) when the resistors are mentioned during the construction.

The 65816 has no SYNC or equivalent but we have to supply this output with a level and IMHO the safest level is (L). AFAIK the only system using SYNC is the KIM-1 and the Elector Junior.

The 65816 also lacks the SO input. The only system I know using the SO-input is one of the Commodore drives: the 1541.


What this all means is that in contrast to a 6502, the 65816 will need some additional glue logic. Definitely required: 74ABT245 - Octal transceiver with direction pin, 20 pin DIP, as a latch for the Bank Address Bus 74ABT541 - Three-state octal bus, 20 pin DIP, as a buffer for the Data Bus 74ABT04 - Inverter, 14 pin, for connecting PHI2 to latch for Bank Address Bus Recommended for some situations, but not necessarily showstoppers: 74ABT74 - D-type Flip-Flop, 14 pin DIP, to sharpen PHI2 waveform 74ABT32 - OR-gate, 14 pin DIP, for address qualification with VDA and VPA. The ABT family is chosen for its speed.

Atari 6502C - Sally (XL/XE:CO14806)

While the Atari 400/800 models contain a generic 6502B CPU (a faster version of the original 6502A microprocessor), all of the XL/XE models contain Atari's customized 6502C chip, known as SALLY.

The SALLY has two pins that differ from the normal 6502. One is that R/W is on a different pin (moved from pin 34 to pin 35). The second pin is the HALT pin (on 36). HALT is used by the ANTIC and GTIA to pause the processor to allow them to access memory (is that correct?).

On the Atari computers, there are two microprocessors, ANTIC and the 6502. To allow them to coexist, ANTIC must shut off the 6502, a process called DMA. The 6502B supports DMA, but in Atari's implementation, it required 4 chips. The 6502C has an extra line called HALT. The /HALT is controlled by ANTIC which uses it whenever it needs the data/address bus. The HALT line is on pin 35 of the Atari 6502C and must be pulled high for the chip to work.

GND pins on SALLY

Information from SAM schematic. Pins 1 (Vss - VP on the 65816 don't GND on 65816), 21 (Vss) and 38 (SO)


Information from SAM schematic. Pin 34 (NC), Pin 7 (NC) and Pin 5 (NC)

Notes from ... What Do I Do With the "Mystery" Pins, SYNC, RDY, S.O., Φ1, MLB, BE, and VPB?

First, rest assured that for simple systems, it is not necessary to understand and use every single pin.  However, here are a few general rules for what to do with the ones whose functions don't interest you.  (There's a forum topic on what to do with the 65816's mystery pins here.)

A pin marked "NC" in the data book means "no connection," so don't connect it.  It's not necessarily a "not-connected" pin.  A few ICs (and I don't know if that includes any 6502-family processors) have internal connections to NC pins but the pin is only used in part of the production testing.  The data sheets usually tell you.  To stay out of trouble, don't use an NC pin for things like a convenient "Y" connection in your wire-wrapping (unless you just cut the pin off the IC itself and only use the WW socket pin).

SYNC:  The "synchronize" output identifies those cycles in which the processor is fetching an op code.  It can be used with the "ready" (RDY) input to single-step the processor.  This will not be covered here, although there is the note about single-cycling the processor in the Clock Generation section. If you don't want to further investigate this possibility through other sources, then leave this pin unconnected.

RDY:  The "ready" input is used for single-stepping, wait states for slow memory, and DMA.  Some makes of 65c02 have had internal weak pull-ups on RDY and other inputs, so you could get away without connecting it to anything.  WDC has apparently removed this.  Better not let it float.  Note that WDC's RDY is bidirectional, and it will be pulled low if it gets the WAI (wait-for-interrupt) instruction in your program.  (WAI puts the processor in a better position to make a fast-as-possible response to an imminent interrupt.)  On the other hand, although you may not have any plans to use WAI, a crash could make the processor misinterpret a $CB operand or data byte as the WAI op code and possibly damage the chip through heating problems if the output is shorted to +5V.  If you don't want to further investigate or use the features this pin is made for, and you want the circuit to be able to handle any manufacturer's 6502 or 65c02, pull it up to +5V through a 3.3K pull-up resistor.

Jeff Laughton has a wait-state circuit on the forum using RDY for slow ROM.

Sometimes it gets called RDY (ready-not), but this is incorrect! RDY would imply that you ground it when you're ready to have the processor move on. It's not that way though.; You ground it when you're not ready yet and need for it to wait. As long as the memory being accessed is always ready at the bus's clock speed, you keep RDY pulled up to mean "I'm ready and I don't need any more time to get the data out." High means, "Yes! Ready! Go!" Low means, "No, I'm not ready!  Don't go yet!"

SO (or SOB):  None of my books' authors seem to know what this set-oVerflow-flag input was intended for, and they just opt to respect its obscurity and don't use it.  It is the most mysterious of all the mystery pins!  Just connect it to +5V.  It could be seen as a 1-bit input with the fastest possible test and branch, but you would have to make sure it never goes low when you need the V bit for its intended purpose of arithmetic operations and testing bits with the BIT instruction.  You will undoubtedly have other input hardware that's more functional anyway.  The Commodore 1541 floppy-disc drive (and relatives) used it, but it was an application that would not be needing it in math routines when the V bit could get set from the outside.

Φ1: (say "phase-one")  This output is commonly left unconnected.  For computers made to the scope of this primer, probably your only reason to use it would be for the RC clock shown in the earlier section Clock Generation.  It is sometimes said to be 180° out of phase with Φ2; but actually Φ2's rising and falling edges will trail Φ1's falling and rising edges (respectively) by a few nanoseconds.

MLB (or ML):  The memory-lock output is generally for multi-processor systems to keep non-optimal bus-arbitration timing from interfering with read-modify-write instructions like ASL, INC, etc..  If you don't want to further investigate this possibility through other sources, then leave this pin unconnected.  You'll only find this pin on WDC's 65c02's anyway, not on those of other manufacturers.

BE:  The bus-enable input allows external control of the buses.  If you don't want to further investigate this possibility through other sources, then pull this up to +5V through a 3.3K resistor.  You'll only find this pin on WDC's 65c02's anyway, not on those of other manufacturers.

VPB (or VP):  The vector-pull output indicates that a vector location is being addressed during an interrupt sequence.  It can be used to select and prioritize interrupts from several sources.  If you don't want to further investigate this possibility through other sources, then leave this pin unconnected.  You'll only find this pin on WDC's 65c02's anyway, not on those of other manufacturers.  Here's the minor conflict associated on the DIP (as opposed to the PLCC or QFP packages:  WDC put the VPB on pin 1 of the DIP, which is one of the two ground pins for other manufacturers.  If you want your board to be compatible with any brand of 6502/65c02, you might want to put a two-pin header to put a shorting block on to connect pin 1 to ground or not.  Unfortunately, such an arrangement will add a little more inductance to the ground connection.  There is another pin for ground (pin 21), but groundbounce and other potentially problematic behaviors on your board could be reduced with non-WDC parts if this pin were directly grounded.  If you want it simple, let me put it this way:  With WDC's 65c02, leave it unconnected.  With anyone else's, ground it.